1. Field of the Invention
The present invention relates to a semiconductor device which is capable of holding a high breakdown voltage, and more particularly, to a dielectric layer isolated semiconductor device.
2. Description of the Prior Art
FIGS. 52 and 53 are a perspective cross sectional view and a cross sectional view, respectively, of a conventional dielectric element isolated semiconductor device 200. On the top and the bottom surfaces of a semiconductor substrate 1, a dielectric layer 3 and a back surface electrode 8 are formed, respectively. An n.sup.- type semiconductor layer 2 is formed on the top surface of the dielectric layer 3. The dielectric layer 3 dielectrically isolates the semiconductor substrate 1 from the n.sup.- type semiconductor layer 2. The n.sup.- type semiconductor layer 2 is delineated by an insulation film 9 into a predetermined region.
In the top surface of the n.sup.- type semiconductor layer 2 at the delineated predetermined region, an n.sup.+ type semiconductor region 4 having a lower resistance than the n.sup.- type semiconductor layer 2 is formed as if surrounded by a p.sup.+ type semiconductor region 5. The n.sup.+ type semiconductor region 4 and the p.sup.+ type semiconductor region 5 are connected respectively to a cathode electrode 6 and an anode electrode 7 which are insulated from each other by an insulation film 11.
FIG. 54 is a cross sectional view showing operations of the conventional dielectric element isolated semiconductor device 200. When the anode electrode 7 and the back surface electrode 8 are kept at 0 V and a gradually increasing positive voltage is given to the cathode electrode 6, a depletion layer 41a grows from a pn junction between the n.sup.- type semiconductor layer 2 and the p.sup.+ type semiconductor region 5. When this happens, since the semiconductor substrate 1 serves through the dielectric layer 3 as a field plate, in addition to the depletion layer 41a, another depletion layer 41b extends from an interface between the n.sup.- type semiconductor layer 2 and the dielectric layer 3 toward the top surface of the n.sup.- type semiconductor layer 2.
The growth of the depletion layer 41b facilitates the expansion of the depletion layer 41a, relieving an electric field at the pn junction between the n.sup.- type semiconductor layer 2 and the p.sup.+ type semiconductor region 5. This phenomena is generally known as RESURF (reduced surface field) effect.
FIG. 55 shows dependence of the electric field strength in a downward direction traversing the thickness of the device on the thickness of the device, the dependence being taken at a point for enough from the p.sup.+ type semiconductor region 5, i.e., at a 55--55 cross section of FIG. 54. In the graph, the thickness (growth) of the depletion layer 41b is x, the thickness of the dielectric layer 3 is t.sub.0, and the origin of the lateral axis is the top surface of the n.sup.- type semiconductor layer 2.
At the 55--55 cross section, a full voltage drop V is expressed as: EQU V=q.multidot.N/( .sub.2 .multidot. .sub.0).multidot.(x.sup.2 /2+ .sub.2 t.sub.0 x/ .sub.3) (1)
where
N: impurity concentration of n type semiconductor layer PA1 .sub.0 : specific inductive capacity in vacuum PA1 .sub.2 : specific inductive capacity of n.sup.- type semiconductor layer 2 PA1 .sub.3 : specific inductive capacity of dielectric layer 3
Eq. 1 indicates that when the full voltage drop V stays unchanged, as the thickness t.sub.0 of the dielectric 1 layer 3 increases, the growth x of the depletion layer 41b decreases. This means that the RESURF effect is weakened.
On the other hand, where there will not be avalanche breakdown due to either field concentration at the pn junction between the n.sup.- type semiconductor layer 2 and the p.sup.+ type semiconductor region 5 or field concentration at an interface between the n.sup.- type semiconductor layer 2 and the n.sup.+ type semiconductor region 4, avalanche breakdown is caused by field concentration at the interface between the n.sup.- type semiconductor layer 2 and the dielectric layer 3 immediately under the n.sup.+ type semiconductor region 4 that eventually determines the breakdown voltage of the semiconductor device 200. To obtain a semiconductor device 200 which satisfies this condition, the distance L between the p.sup.+ type semiconductor region 5 and the n.sup.+ type semiconductor region 4 has to be long enough and the thickness d and the impurity concentration N of the n.sup.- type semiconductor layer 2 have to be optimum.
FIG. 56 is a cross sectional view showing operations of the conventional dielectric element isolated semiconductor device 200 which satisfies such a condition above. It is generally known that field concentration created at the interface between the n.sup.- type semiconductor layer 2 and the dielectric layer 3 satisfies the avalanche condition precisely when the n.sup.- type semiconductor layer 2 has been depleted from its interface, with the dielectric layer 3 to its surface. In FIG. 56, the depletion layer 41 has reached the n.sup.+ type semiconductor region 4, completely depleting the n.sup.- type semiconductor layer 2.
When dielectric element isolated semiconductor device 200 assumes such a condition, where the thickness of the n.sup.+ type semiconductor region 4 is not considered, the breakdown voltage V is expressed as: EQU V=E.sub.cr .multidot.(d/2+ .sub.2 .multidot.t.sub.0 / .sub.3)(2)
where E.sub.cr : critical electrical field for causing avalanche
FIG. 57 shows dependence of the electric field strength in a downward direction traversing the thickness of the device on the thickness of the device, the dependence being taken immediately under the n.sup.+ type semiconductor region 4, i.e., across line 57--57 of FIG. 56. The graph indicates that critical electrical field E.sub.cr is reached at the interface between the n.sup.- type semiconductor layer 2 and the dielectric layer 3 (i.e., at a distance d from the origin toward the electrode 8).
The breakdown voltage of the dielectric element isolated semiconductor device 200 will now be calculated assuming that the n.sup.- type semiconductor layer 2 is made of silicon and the dielectric layer 3 is formed by a silicon oxide film. As is standard in the art, d=4.times.10.sup.-4 and t.sub.0 =2.times.10.sup.-4. The critical electrical field E.sub.cr, which is sensitive to the thickness d of the n.sup.- type semiconductor layer 2, is about E.sub.cr =4.times.10.sup.5 in this case. Substituting these values, .sub.2 =11.7 and .sub.3 =3.9 in Eq. 2, the breakdown voltage V is: EQU V.apprxeq.320[V] (3)
Hence, if the thickness d of the n.sup.- type semiconductor layer 2 increases 1 .mu.m, the breakdown voltage increases by: EQU .DELTA.V=E.sub.cr .times.0.5.times.10.sup.-4 =20[V] (4)
On the other hand, with a 1 .mu.m increase in the thickness t.sub.0 of the dielectric layer 3, the breakdown voltage increases by: EQU .DELTA.V=E.sub.cr .times.11.7.times.1.times.10.sup.-4 /3.9=120[V](5)
It then follows that greater improvement in the breakdown voltage would be attained if the dielectric layer 3 is thickened than if the n.sup.- type semiconductor layer 2 is thickened. Thus, to form the dielectric layer 3 thick is effective in enhancing the breakdown voltage. Equally important, increase in the thickness of the n.sup.- type semiconductor layer 2 is not desirable also in terms of ease of forming the insulation film 9.
However, when the thickness to of the dielectric layer 3 is increased, the growth x of the depletion layer 41b and hence the RESURF effect would be suppressed. In other words, when the dielectric layer 3 gains thickness, the field concentration at the pn junction between the n.sup.- type semiconductor layer 2 and the p.sup.+ type semiconductor region 5 increased, causing avalanche breakdown thereat which would limit the breakdown voltage.
Since the conventional semiconductor device has such a construction, the breakdown voltage of the semiconductor device is limited by the thickness of the dielectric layer 3 and the thickness of the n.sup.- type semiconductor layer 2.